Semiconductor memory device and memory controller

ABSTRACT

A semiconductor memory device includes memory cells, word lines, and a row decoder. When program verification is performed on a memory cell that has been programmed, the row decoder transfers a first voltage to word lines that are electrically connected to gates of first memory cells. Also, when data is read, the row decoder selects a word line electrically connected to gates of selected memory cells, transfers the first voltage to non-selected word lines that are electrically connected to the first memory cells, and transfers a second voltage, which is higher than the first voltage, to non-selected word lines that are electrically connected to second memory cells.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2014-052706, filed on Mar. 14, 2014, theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor memorydevice and a memory controller.

BACKGROUND

A NAND flash memory in which memory cells are three-dimensionallyarranged is known.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a memory system according to anembodiment.

FIG. 2 is a block diagram illustrating a semiconductor memory deviceaccording to the embodiment.

FIG. 3 is a circuit diagram illustrating a memory cell array accordingto the embodiment.

FIG. 4 is a cross-sectional view illustrating the memory cell arrayaccording to the embodiment.

FIG. 5 is a schematic diagram illustrating a write state table accordingto the embodiment.

FIG. 6 is a circuit diagram illustrating a string unit according to theembodiment.

FIG. 7 is a timing chart illustrating various signals when a writeoperation according to the embodiment is performed.

FIG. 8 is a graph illustrating the threshold distribution of the memorycells according to the embodiment.

FIG. 9 is a circuit diagram illustrating a NAND string according to theembodiment.

FIG. 10 is a circuit diagram illustrating a NAND string according to theembodiment.

FIG. 11 is a timing chart illustrating various signals when a readoperation according to the embodiment is performed.

FIG. 12 is a circuit diagram illustrating a NAND string according to theembodiment.

FIG. 13 is a timing chart illustrating various signals when an eraseoperation according to the embodiment is performed.

FIG. 14 is a circuit diagram illustrating a NAND string according to theembodiment.

FIG. 15 is a circuit diagram illustrating a NAND string according to theembodiment.

FIG. 16 is a circuit diagram illustrating a NAND string according to theembodiment.

FIG. 17 is a circuit diagram illustrating a NAND string.

FIG. 18 is a circuit diagram illustrating a NAND string.

FIG. 19 is a circuit diagram illustrating a NAND string.

FIG. 20 is a circuit diagram illustrating a NAND string.

FIG. 21 is a schematic diagram illustrating information held in a writestate table according to a modification example.

FIG. 22 is a circuit diagram illustrating the NAND string according tothe modification example.

FIG. 23 is a circuit diagram illustrating the NAND string according tothe modification example.

FIG. 24 is a circuit diagram illustrating the NAND string according tothe modification example.

DETAILED DESCRIPTION

The present embodiment now will be described more fully hereinafter withreference to the accompanying drawings, in which various embodiments areillustrated. In the drawings, the thickness of layers and regions may beexaggerated for clarity. Like numbers refer to like elements throughout.As used herein the term “and/or” includes any and all combinations ofone or more of the associated listed items and may be abbreviated as“/”.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a,” “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “having,” “includes,” “including” and/or variationsthereof, when used in this specification, specify the presence of statedfeatures, regions, steps, operations, elements, and/or components, butdo not preclude the presence or addition of one or more other features,regions, steps, operations, elements, components, and/or groups thereof.

It will be understood that when an element such as a layer or region isreferred to as being “on” or extending “onto” another element (and/orvariations thereof), it may be directly on or extend directly onto theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly on” or extending“directly onto” another element (and/or variations thereof), there areno intervening elements present. It will also be understood that when anelement is referred to as being “connected” or “coupled” to anotherelement (and/or variations thereof), it may be directly connected orcoupled to the other element or intervening elements may be present. Incontrast, when an element is referred to as being “directly connected”or “directly coupled” to another element (and/or variations thereof),there are no intervening elements present.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, components, regions, layersand/or sections, these elements, materials, regions, layers and/orsections should not be limited by these terms. These terms are only usedto distinguish one element, material, region, layer or section fromanother element, material, region, layer or section. Thus, a firstelement, material, region, layer or section discussed below could betermed a second element, material, region, layer or section withoutdeparting from the teachings of the present invention.

Relative terms, such as “lower”, “back”, and “upper” may be used hereinto describe one element's relationship to another element as illustratedin the Figures. It will be understood that relative terms are intendedto encompass different orientations of the device in addition to theorientation depicted in the Figures. For example, if the structure inthe Figure is turned over, elements described as being on the “backside”of substrate would then be oriented on “upper” surface of the substrate.The exemplary term “upper”, may therefore, encompass both an orientationof “lower” and “upper,” depending on the particular orientation of thefigure. Similarly, if the structure in one of the figures is turnedover, elements described as “below” or “beneath” other elements wouldthen be oriented “above” the other elements. The exemplary terms “below”or “beneath” may, therefore, encompass both an orientation of above andbelow.

Embodiments are described herein with reference to cross sections andperspective illustrations that are schematic illustrations ofembodiments. As such, variations from the shapes of the illustrations asa result, for example, of manufacturing techniques and/or tolerances,are to be expected. Thus, embodiments should not be construed as limitedto the particular shapes of regions illustrated herein but are toinclude deviations in shapes that result, for example, frommanufacturing. For example, a region illustrated or described as flatmay, typically, have rough and/or nonlinear features. Moreover, sharpangles that are illustrated, typically, may be rounded. Thus, theregions illustrated in the figures are schematic in nature and theirshapes are not intended to illustrate the precise shape of a region andare not intended to limit the scope of the present invention.

A semiconductor memory device which is capable of improving performanceand a memory controller are provided.

In general, according to one embodiment, there is provided asemiconductor memory device including a plurality of memory cells thatare stacked above a semiconductor substrate and are electricallyconnected in series, a plurality of word lines that are electricallyconnected to gates of the memory cells, and a row decoder that iselectrically connected to the word lines. When data is read, the rowdecoder selects a word line, transfers a first voltage to non-selectedword lines that are electrically connected to first memory cells, andtransfers a second voltage, which is different from the first voltage,to non-selected word lines which are electrically connected to secondmemory cells.

Hereinafter, embodiments will be described with reference to theaccompanying drawings. Meanwhile, common reference numerals are attachedto components having the same functions and configurations in thedescription below.

A semiconductor memory device and a memory controller according to anembodiment will be described. Hereinafter, a 3-dimensional stacked NANDflash memory, in which memory cells are stacked on the upper side of asemiconductor substrate, will be described as an example of thesemiconductor memory device.

1. CONFIGURATION

1. 1 Configuration of Memory System

First, the configuration of a memory system which includes asemiconductor memory device according to an embodiment will be describedwith reference to FIG. 1. FIG. 1 is a block diagram illustrating thememory system according to the embodiment.

A memory system 1 includes a NAND flash memory 100 and a memorycontroller 200 as illustrated in the drawing. The controller 200 and theNAND flash memory 100 may form a single semiconductor device through,for example, the combination thereof. A memory card, such as an SD™card, a Solid State Drive (SSD), or the like may be used as an exampleof the single semiconductor device.

The NAND flash memory 100 includes a plurality of memory cells, andstores data in a non-volatilization manner. The configuration of theNAND flash memory 100 will be described in detail below.

The controller 200 instructs the NAND flash memory 100 to perform read,write, erase, or the like in response to an instruction from externalhost equipment. In addition, the controller 200 manages a memory spaceof the NAND flash memory 100.

The controller 200 includes a host interface circuit 210, a built-inmemory (RAM) 220, a processor (CPU) 230, a buffer memory 240, a NANDinterface circuit 250, and an ECC circuit 260.

The host interface circuit 210 is connected to host equipment through acontroller bus, and communicates with the host equipment. Further, thehost interface circuit 210 transfers an instruction and data, which arereceived from the host equipment, the CPU 230 and the buffer memory 240,respectively. In addition, the host interface circuit 210 transfers datain the buffer memory 240 to the host equipment in response to theinstruction of the CPU 230.

The NAND interface circuit 250 is connected to the NAND flash memory 100through a NAND bus, and communicates with the NAND flash memory 100.Further, the NAND interface circuit 250 transfers the instruction, whichis received from the CPU 230, to the NAND flash memory 100. In addition,when write is performed, the NAND interface circuit 250 transfers writedata in the buffer memory 240 to the NAND flash memory 100. Further,when data is read, the NAND interface circuit 250 transfers data whichis read from the NAND flash memory 100 to the buffer memory 240.

The CPU 230 controls the entire operation of the controller 200. Forexample, when the CPU 230 receives a write instruction from the hostequipment, the CPU 230 issues the write instruction based on the NANDinterface in response thereto. The CPU 230 performs the same operationwhen data is read or the data is erased. In addition, the CPU 230performs various processes, such as wear leveling, in order to managethe NAND flash memory 100. Further, the CPU 230 performs variouscalculations. For example, the CPU 230 performs a data encryptionprocess, a randomization process, and the like.

The ECC circuit 260 performs a data Error Checking and Correcting (ECC)process. That is, when data is written, the ECC circuit 260 generatesparity data based on write data. When data is read, the ECC circuit 260detects an error by generating a syndrome from the parity data, andcorrects the error. Meanwhile, the CPU 230 may include the function ofthe ECC circuit 260.

The built-in memory 220 is, for example, a semiconductor memory such asa DRAM, and is used as the work area of the CPU 230. Further, thebuilt-in memory 220 holds firmware, various management tables, and thelike in order to manage the NAND flash memory 100. In addition, thebuilt-in memory 220 holds a write state table 270 which is related tothe NAND flash memory 100. The write state table 270 is informationindicative of a page up to which data is written in a string unit SUwhich will be described later. Further, the CPU 230 issues a data readinstruction or an erase instruction with reference to the information inthe write state table 270. The write state table 270 will be describedin detail in a category of 1.3.

1.2 Configuration of NAND Flash Memory

Subsequently, the configuration of the NAND flash memory 100 will bedescribed.

1. 2. 1 Configuration of NAND Flash Memory 100

FIG. 2 is a block diagram illustrating the NAND flash memory 100according to the embodiment. The NAND flash memory 100 includes a memorycell array 111, a row decoder 112, a sense amplifier 113, a source linedriver 114, a well driver 115, a sequencer 116, and a register 117 asillustrated in the drawing.

The memory cell array 111 includes a plurality of blocks BLK (BLK0,BLK1, BLK2, . . . ) each of which is a set of a plurality of nonvolatilememory cells associated with word lines and bit lines. The block BLK isa data erase unit, and data in the same block BLK is collectivelyerased. Each block BLK includes a plurality of string units SU (SU0,SU1, SU2, . . . ) each of which is a set of NAND strings 118 in whichthe memory cells are connected in series. It is apparent that the numberof blocks in the memory cell array 111 and the number of string units ina single block BLK are arbitrary.

The row decoder 112 decodes a block address or a page address, andselects any one of word lines of a relevant block. Further, the rowdecoder 112 applies an appropriate voltage to the selected word line andnon-selected word lines.

When data is read, the sense amplifier 113 senses and amplifies dataread to a bit line from the memory cells. In addition, when data iswritten, the sense amplifier 113 transfers the write data to the memorycells. The data is read from and written to the memory cell array 111 inunits of a plurality of memory cells, and the units form a page.

The source line driver 114 applies a voltage to source lines.

The well driver 115 applies a voltage to a well region in which the NANDstrings 118 is formed.

The register 117 holds various data. For example, the register 117 holdsthe statuses of the data write and erase operations that indicatewhether or not the operation of the controller is normally completed.Otherwise, the register 117 holds a command, an address, and the likewhich is received from the controller 200. In addition, the register 117may hold various tables.

The sequencer 116 controls the entire operation of the NAND flash memory100.

1.2.2 Memory Cell Array 111

Subsequently, the configuration of the memory cell array 111 will bedescribed in detail. FIG. 3 is a circuit diagram illustrating any one ofthe blocks BLK and other blocks BLK have the same configuration.

As illustrated in the drawing, the block BLK includes, for example, fourstring units SU (SU0 to SU3). In addition, each of the string units SUincludes a plurality of NAND strings 118.

Each of the NAND strings 118 includes, for example, eight memory celltransistors MT (MT0 to MT7), and select transistors ST1 and ST2. Each ofthe memory cell transistors MT includes a stacked gate, which has acontrol gate and a charge storage layer, and holds data in non-volatilemanner. Meanwhile, the number of memory cell transistors MT is notlimited to eight, and may be 16, 32, 64, 128, or the like, that is, isnot limited to any particular number. The memory cell transistors MT arearranged between the select transistors ST1 and ST2 such that thecurrent paths thereof are connected in series. The current path of thememory cell transistor MT7 which is on one end side of the serialconnection is connected to one end of the current path of the selecttransistor ST1, and the current path of the memory cell transistor MT0which is on the other end side is connected to one end of the currentpath of the select transistor ST2.

The gates of the select transistors ST1 of the respective string unitsSU0 to SU3 are connected to respective select gate lines SGD0 to SGD3.In contrast, the gates of the select transistors ST2 are commonlyconnected to the same select gate line SGS between the plurality ofstring units. In addition, the control gates of the respective memorycell transistors MT0 to MT7 in the same block BLK0 are commonlyconnected to word lines WL0 to WL7, respectively.

That is, the word lines WL0 to WL7 and the select gate line SGS arecommonly connected between the plurality of string units SU0 to SU3 inthe same block BLK. In contrast, the select gate lines SGD areindependent from each other for the respective string units SU0 to SU3even in the same block BLK.

In addition, from among the NAND strings 118 which are arranged in amatrix shape in the memory cell array 111, the other ends of the currentpaths of the select transistors ST1 of the NAND strings 118 in the samerow are commonly connected to any one of bit lines BL (BL0 to BL(L−1),(L−1) is a natural number which is equal to or greater than 1). That is,the bit lines BL commonly connect the NAND strings 118 between theplurality of blocks BLK. In addition, the other ends of the currentpaths of the select transistors ST2 are commonly connected to a sourceline SL. The source line SL is commonly connected to, for example, theNAND strings 118 between the plurality of blocks.

As described above, the data of the memory cell transistors MT in thesame block BLK is collectively erased. In contrast, data is collectivelyread and written with regard to the plurality of memory cell transistorsMT which are commonly connected to any one of the word lines WL in anyone of the string units SU of any one of the blocks BLK. The unit ofreading and writing is called a “page”.

FIG. 4 is a cross-sectional view illustrating a partial area of thememory cell array 111 according to the embodiment. As illustrated in thedrawing, the plurality of NAND strings 118 are formed on a p-type wellregion 20. That is, on the well region 20, a plurality of wire layers 27which function as the select gate lines SGS, a plurality of wire layers23 which function as the word lines WL, and a plurality of wire layers25 which function as the select gate lines SGD are formed.

Further, a memory hole 26 which reaches the well region 20 through thewire layers 25, 23, and 27 is formed. A block insulating film 28, acharge storage layer 29 (insulating film), and a gate insulating film 30are sequentially formed on the side surface of the memory hole 26.Further, a conductive film 31 is embedded in the memory hole 26. Theconductive film 31 functions as the current path of the NAND string 118,and forms the channel area when the memory cell transistors MT and theselect transistors ST1 and ST2 are operated.

In each NAND string 118, the wire layers 27 which are provided in plural(in the example, 4 layers) are electrically connected in common and areconnected to the same select gate line SGS. That is, the four-layeredwire layers 27 substantially function as a gate electrode of a singleselect transistor ST2. This is the same as in the select transistor ST1(four-layered select gate line SGD).

In such a configuration, in each NAND string 118, the select transistorST2, the plurality of memory cell transistors MT, and the selecttransistor ST1 are sequentially stacked on the well region 20.

Meanwhile, in the example of FIG. 4, the select transistors ST1 and ST2include the charge storage layers 29 similarly to the memory celltransistors MT. However, the select transistors ST1 and ST2 do notsubstantially function as memory cells which hold data but function asswitches. At this time, thresholds which cause the select transistorsST1 and ST2 to be turned on or off may be controlled by injectingcharges into the charge storage layer 29.

A wire layer 32 which functions as the bit line BL is formed on theupper end of the conductive film 31. The bit line BL is connected to thesense amplifier 113.

Further, an n⁺ dopant diffusion layer 33 and a p⁺ dopant diffusion layer34 are formed on the surface of the well region 20. A contact plug 35 isformed on the diffusion layer 33, and a wire layer 36 which functions asthe source line SL is formed on the contact plug 35. The source line SLis connected to the source line driver 114. In addition, a contact plug37 is formed on the diffusion layer 34, and a wire layer 38 whichfunctions as a well wiring CPWELL is formed on the contact plug 37. Thewell wiring CPWELL is connected to the well driver 115. The wire layers36 and 38 are formed on a layer which is an upper layer than the selectgate line SGD and is a lower layer than the wire layer 32.

The above configuration is arranged in plural in the depth direction ofa paper in which FIG. 4 is illustrated, and the string units SU areformed by sets of the plurality of NAND strings 118 which are arrangedin the depth direction. In addition, the wire layers 27, which functionas the plurality of select gate lines SGS included in the same stringunit SU, are commonly connected to each other. That is, the gateinsulating film 30 is formed even on the well region 20 between theadjacent NAND strings 118, the wire layer 27 and the gate insulatingfilm 30 which are adjacent to the diffusion layer 33 are formed up tothe vicinity of the diffusion layer 33.

Therefore, when the select transistor ST2 is caused to be an on state,the channel thereof electrically connects the memory cell transistor MT0to the diffusion layer 33. In addition, it is possible to give apotential to the conductive film 31 by applying a voltage to the wellwiring CPWELL.

Meanwhile, other configurations may be used as the configuration of thememory cell array 111. That is, the configuration of the memory cellarray 111 is disclosed in, for example, U.S. patent application Ser. No.12/407,403 “Three dimensional stacked nonvolatile semiconductor memory”which is applied Mar. 19, 2009, U.S. patent application Ser. No.12/406,524 “Three dimensional stacked nonvolatile semiconductor memory”which is applied Mar. 18, 2009, U.S. patent application Ser. No.12/679,991 “Non-volatile semiconductor storage device and method ofmanufacturing the same” applied Mar. 25, 2010, and U.S. patentapplication Ser. No. 12/532,030 “Semiconductor memory and method formanufacturing the same” which is applied Mar. 23, 2009. All of thepatent applications are incorporated by reference herein.

1.3 Write State Table 270

Subsequently, the write state table 270 illustrated in FIG. 1 will bedescribed. FIG. 5 is a schematic diagram illustrating the write statetable 270.

As illustrated in the drawing, the table 270 holds informationindicative of word lines WL (in other words, a page) to which the datais written in each string unit SU of each block BLK. Normally, in theNAND flash memory, data is sequentially written from a source-sidememory cell transistor MT. Therefore, the example of FIG. 5 illustratesthat data is written in the memory cell transistors which are connectedto the word lines WL0 to WL2 in the string unit SU0 of the block BLK0,and that the memory cell transistors which are connected to the wordlines WL3 to WL7 are in an erase state. The situation is illustrated inFIG. 6. In addition, in the string unit SU1 of the block BLK1, it isillustrated that data is written in the word lines WL0 to WL7, that is,in the whole memory cell transistors MT.

The CPU 230 of the memory controller 200 updates the write state table270 whenever data is written in the NAND flash memory 100 or wheneverdata is copied between the blocks.

2. DATA WRITE OPERATION

Subsequently, a data write operation according to the embodiment will bedescribed.

2.1 Signals on NAND Bus

First, signals which are transmitted and received on the NAND Busbetween the NAND flash memory 100 and the controller 200 will bedescribed with reference to FIG. 7. FIG. 7 is a timing chartillustrating various signals acquired when data is written. In thedrawing, a chip enable signal /CE, an address latch enable signal ALE, acommand latch enable signal CLE, a write enable signal /WE, a readenable signal /RE, an input/output signal I/O, and a ready/busy signalR/B are signals which are transmitted and received between thecontroller 200 and the NAND flash memory 100.

/CE is a signal for enabling the NAND flash memory 100, and is enabledand asserted at a Low level. ALE is a signal for providing anotification that an input signal is an address signal to the NAND flashmemory. CLE is a signal for providing a notification that the inputsignal is a command to the NAND flash memory. /WE is a signal forcausing the input signal to be supplied to the NAND flash memory 100.The signal R/B is a signal for indicating whether the NAND flash memory100 is in a ready state (state in which a signal may be received) or ina busy state (state in which it cannot receive a signal) for thecontroller 200.

As illustrated in the drawing, the controller 200 first issues a writecommand “80H” and asserts CLE (“H” level). Subsequently, the controller200 issues column addresses (CA0 to CA11) for two cycles, and assertsALE (“H” level). Sequentially, the controller 200 issues page addresses(PA0 to PA16) for three cycles. The command and addresses are stored,for example, in the register 117 of the NAND flash memory 100.

Thereafter, the controller 200 outputs data Din for a plurality ofcycles. Meanwhile, ALE and CLE are negated (“L” level). At last, thecontroller 200 issues a write command “10H” and asserts CLE. Wheneverthe controller 200 issues a command, an address, data and the like, thecontroller 200 asserts /WE. Accordingly, whenever /WE is toggled, thesignals are supplied to the NAND flash memory 100.

The NAND flash memory 100 starts a write operation in response to thecommand “10H” and is in a busy state (R/B=“L”).

If the write operation is completed in the NAND flash memory 100, R/Breturns to an “H” level. Thereafter, the controller 200 issues a statusread command “70H”, and reads status, which indicates whether or notdata is successfully written, from the register 117.

2.2 Threshold Distribution

FIG. 8 is a graph illustrating the threshold distribution of the memorycell transistor MT. In the example, an example in which the memory celltransistor is capable of holding data of one bit (2 values) isdescribed. However, the memory cell transistor may be capable of holdingdata of two bits (4 values) or more.

As illustrated in the drawing, the thresholds of the memory celltransistors MT in the erase state are smaller than those in an eraseverification level Vev, and may be negative values or positive values.The thresholds of the memory cell transistors MT in the write state aregreater than those in a program verification level Vpv (Vpv>Vev), andhave, for example, a positive value.

When data is written and read, a voltage VPVD (for example, 4 V), VREAD(for example, 7V), VPASS (for example, 8 to 9 V), and VPGM (for example,20 V), or the like is used, and there is a relationship in whichVpv<VPVD<VREAD<VPASS<VPGM.

2.3 Operation of NAND Flash Memory 100

Subsequently, an operation of the NAND flash memory 100 when the writeoperation is performed will be described. The write operation generallyincludes a programming operation to raise thresholds by injecting chargeinto the charge storage layer, and a program verification operation torecognize thresholds which change as a result of the programmingoperation. Further, data is written in a page unit by repeating a set ofthe operations. The operations are mainly performed under the control ofthe sequencer 116. Meanwhile, an operation to maintain the thresholds ofthe memory cell transistors MT at an “E” level is called a “1” write,and an operation to raise the thresholds from the “E” level to a “P”level is called a “0” write.

FIG. 9 is a circuit diagram illustrating the NAND string 118 whenprogramming is performed. As illustrated in the drawing, the row decoder112 applies the voltage VPGM to a selected word line WL1 and applies thevoltage VPASS to the other non-selected word lines WL0 and WL2 to WL7.VPGM is a high voltage for injecting charge into the charge storagelayer through FN tunneling, and VPASS is a voltage which is capable ofsuppressing the non-selected memory cell transistors from beingerroneously written in the NAND string which is a target to be writtenwith “0”, and is capable of boosting a voltage of a channel due tocoupling to the extent that the thresholds in the selected memory celltransistors MT are suppressed from rising in the NAND string in a statein which “1” is written.

In addition, the row decoder 112 causes the select transistor ST2 to beturned off by applying 0 V to the select gate line SGS. In addition, therow decoder 112 applies VSGD to the select gate line SGD. As a result,in a bit line BL (for example, 0 V is given) in which “0” is written,the select transistor ST1 is in an on state, and the potential of thebit line is transferred to the channels of the memory cell transistorsMT. Therefore, data is programmed in the selected memory cell transistorMT1. In the bit line BL on the other side in which “1” is written (forexample, positive potential is given), the select transistor ST1 is in acut-off state. As a result, the channels of the memory cell transistorsMT are in an electrically floating state, and the data is notprogrammed.

FIG. 10 is a circuit diagram illustrating the NAND string 118 acquiredwhen program verification is performed. As illustrated in the drawing,the row decoder 112 applies a program verification voltage Vpv to theselected word line WL1, applies a voltage VREAD or VREADK to thenon-selected word line WL0 which has been already programmed, applies avoltage VREAD, VREADK, or VPVD to the non-selected word line WL2,applies a voltage VREAD to the non-selected word line WL3, and appliesthe voltage VPVD to the other non-selected word lines WL4 to WL7. VREADand VPVD are voltages for causing the memory cell transistors MT to beturned on regardless of held data, and there is a relationship in whichVREAD>VPVD. Although VREADK is normally greater than VREAD, VREADK maybe smaller than VREAD. VREADK is a voltage for preventing erroneous readdue to word lines which are come into contact with the selected wordline.

A further detailed example of a voltage, which is applied to the wordlines WL when the program verification is performed, will be describedbelow. For example, it is assumed that the number of word lines in thestring unit SU is N+1 (N is a natural number which is equal to orgreater than 6) and WLn (n is any one of 0 to N) is a selected wordline.

In this case, a program verification voltage Vpv is applied to the wordline WLn. Further, VREAD or VREADK is applied to a word line WL (n−1)which is on a further source side than the selected word line WLn, andVREAD is applied to word lines WL0 to WL (n−2).

On the other hand, VREAD or VREADK is applied to a word line WL(n+1)which is on a further drain side than the selected word line WLn, VREADis applied to WL(n+2), and VPVD is applied to WL(n+3) to WLN.

In addition, the row decoder 112 applies VSG to the select gate linesSGD and SGS, and causes the select transistors ST1 and ST2 to be turnedon. As a result, if the memory cell transistor MT1 which is connected tothe selected word line WL1 is turned on, cell current Icell1 flows fromthe bit line BL to the source line SL. The sense amplifier 113 performssense amplification on the cell current and reads data.

3. DATA READ OPERATION

Subsequently, a data read operation according to the embodiment will bedescribed.

3.1 Signals on NAND Bus

First, signals which are transmitted and received on the NAND busbetween the NAND flash memory 100 and the controller 200 will bedescribed with reference to FIG. 11. FIG. 11 is a timing chartillustrating various signals acquired when data is read.

As illustrated in the drawing, the controller 200 first issues a writestate transmission command “XXH” and asserts CLE. Sequentially, the CPU230 of the controller 200 reads information indicative of a word line WL(in other words, page), in which data is written, in the string unit SUwhich is a read target with reference to the write state table in thebuilt-in memory 220, and transfers the information (“INF0” and “INF1”)to the NAND flash memory 100. Meantime, the signal ALE is asserted. Thepieces of information “INF0” and “INF1” are stored in, for example, theregister 117.

Thereafter, the controller 200 issues a read command “00H” and assertsCLE. Subsequently, the controller 200 issues a column address and a pageaddress as the same as when the write operation is performed. Thecommand and the address are also stored in, for example, the register117. Further, the controller 200 issues a read command “30H” at last.

The NAND flash memory 100 starts the read operation in response to thecommand “30H”, and is in the busy state (R/B=“L”).

Thereafter, if the NAND flash memory 100 returns to a ready state, readdata is transferred from the NAND flash memory 100 to the controller 200whenever /RE is asserted.

3.2 Operation of NAND Flash Memory 100

Subsequently, the operation of the NAND flash memory 100 when the readoperation is performed will be described. FIG. 12 is a circuit diagramillustrating the NAND string 118 when the read operation is performed.FIG. 12 illustrates a case in which data has been already written in thememory cell transistors MT which are connected to the word lines WL0 toWL3, and in which data has not been written yet in the memory celltransistors MT which are connected to the word lines WL4 to WL7 (erasestate).

As illustrated in the drawing, the row decoder 112 applies a voltageVCGRV to a selected word line WL1. VCGRV is a voltage for reading datafrom the selected memory cell. In addition, the row decoder 112 appliesa voltage VREAD or VREADK to non-selected word lines WL0 and WL2 inwhich data has been already written, and applies a voltage VREAD to theword line WL3. Further, the row decoder 112 applies a voltage VPVD,which is used when program verification is performed, to the word linesWL4 to WL7 in which data has not been written yet. It is possible todetermine a word line WL, to which the VREAD is applied, and a word lineWL, to which the VPVD is applied, is such a way that, for example, thesequencer 116 refers to the information “INF0” and “INF1” in theregister 117.

Further, the row decoder 112 applies VSG to the select gate lines SGDand SGS, and causes the select transistors ST1 and ST2 to be turned on.As a result, if the memory cell transistor MT1 which is connected to theselected word line WL1 is turned on, cell current Icell2 flows from thebit line BL to the source line SL. The sense amplifier 113 senses andamplifies the cell current, and reads data.

A further detailed example of a voltage, which is applied to the wordline WL when the read operation is performed will be described below.For example, it is assumed that the number of word lines in the stringunit SU is N+1 (N is a natural number which is equal to or greater than6), WLn (n is any one of 0 to N) is a selected word line, and data iswritten in word lines WL0 to WLm (m is a natural number which is equalto or greater than n, n<<m).

In this case, a read voltage VCGRV is applied to the word line WLn.Further, VREAD or VREADK is applied to word lines WL(n−1) and WL(n+1)which are adjacent to the selected word line WLn, VREAD is applied toword lines WL0 to WL(n−2) and a word line WL(n+2), VREAD is applied toword lines WL(n+3) to WLm, and VPVD is applied to word lines WL(m+1) toWLN.

4. DATA ERASE OPERATION

Subsequently, a data erase operation according to the embodiment will bedescribed.

4.1 Signals on NAND Bus

First, signals which are transmitted and received on the NAND busbetween the NAND flash memory 100 and the controller 200 will bedescribed with reference to FIG. 13. FIG. 13 is a timing chartillustrating various signals acquired during a data erase operation.

As illustrated in the drawing, the controller 200 first transfers awrite state transmission command “XXH” and information “INF0” and “INF1”to the NAND flash memory 100 as the same as when data is read.

Thereafter, the controller 200 issues an erase command “60H” andtransfers the block address of the block BLK which is an erase target.The command and the address are also stored in, for example, theregister 117. Further, the controller 200 issues an erase command “D0H”at last.

The NAND flash memory 100 starts a read operation in response to thecommand “D0H” and is in a busy state (R/B=“L”).

If the write operation is completed in the NAND flash memory 100, R/Breturns to the “H” level. Thereafter, the controller 200 issues a statusread command “70H” and reads a status, which indicates whether or notthe data is successfully erased, from the register 117.

4.2 Operation performed by NAND Flash Memory 100

Subsequently, an operation performed by the NAND flash memory 100 whenthe erase operation is performed will be described. The erase operationgenerally includes a data erase operation to lower the thresholds byabstracting charges from the charge storage layer or injecting a holeinto the charge storage layer, and an erase verification operation torecognize change in the threshold distribution as a result of the dataerase operation. Further, the data is erased, for example, in a blockunit (or a string unit or the like) by repeating a set of theoperations.

FIG. 14 is a circuit diagram illustrating the NAND string 118 when datais erased. FIG. 14 illustrates a case in which data has been alreadywritten in the memory cell transistors MT connected to the word linesWL0 to WL3 and in which data has not been written yet in the memory celltransistors MT connected to the word lines WL4 to WL7 (has been alreadyin an erase state).

As illustrated in the drawing, the row decoder 112 applies a voltage V1(for example, 0 V) to all of the word lines WL0 to WL7. In addition, thewell driver 115 applies an erase voltage VERA (a positive voltage of,for example, 20 V) to the well region 20. As a result, charges in thecharge storage layer are drawn to the conductive film 31, and thus thethresholds of the memory cell transistors MT are lowered.

FIG. 15 is a circuit diagram illustrating the NAND string 118 when eraseverification is performed. As illustrated in the drawing, the rowdecoder 112 applies an erase verification voltage Vev1 to non-selectedword lines WL0 to WL3 in which data has been already written. Further,the row decoder 112 applies an erase verification voltage Vev2 (<Vev1)to word lines WL4 to WL7 in which data has not been written yet. It ispossible to determine a word line WL to which Vev1 is applied and a wordline WL to which Vev2 is applied in such a way that, for example, thesequencer 116 refers to the information “INF0” and “INF1” of theregister 117.

Further, the row decoder 112 causes the select transistors ST1 and ST2to be turned on by giving VSG to the select gate lines SGD and SGS. As aresult, if all of the memory cell transistors MT0 to MT7 which areconnected to the word lines WL0 to WL7 are turned on, that is, if thethresholds of the memory cell transistors MT are lowered to a desiredvalue, cell current Icell3 flows from the bit line BL to the source lineSL. The sense amplifier 113 senses and amplifies the cell current andreads data.

Meanwhile, in the data erase operation which is described with referenceto FIG. 14, the voltage which is applied to the word line WL may bechanged according to whether or not write was completed. Such an exampleis illustrated in FIG. 16. FIG. 16 is a circuit diagram illustrating theNAND string 118 acquired when the data erase operation is performed. Asillustrated in the drawing, the row decoder 112 may apply the voltage V1to non-selected word lines WL0 to WL3 in which data has been alreadywritten, and may apply the voltage V2 (>V1) to word lines WL4 to WL7.

5. ADVANTAGES ACCORDING TO EMBODIMENT

As described above, in the semiconductor memory device according to theembodiment, a voltage, which is applied to the word line WL when thewrite operation and the erase operation are performed, is set accordingto a word line of the NAND string 118 to which data is written.Therefore, it is possible to improve the performance of the NAND flashmemory. Hereinafter, the advantages will be described with reference toFIGS. 17 to 20. FIGS. 17 to 20 are circuit diagrams illustrating theNAND string.

When the program verification is performed, an application voltage whichis generally considered is as illustrated in FIG. 17. That is, VREAD isapplied to all of the non-selected word lines WL. In this case, forexample, when the memory cell transistor MT1 is a write target, thememory cell transistors which are connected to the memory celltransistors MT2 to MT7 on the further drain side are in the erase state.That is, since the thresholds of the memory cell transistors MT2 to MT7are sufficiently low, relatively high cell current Icell4 flows.

Subsequently, FIG. 18 illustrates a situation in which data is read fromthe memory cell transistor MT1 after data is written in the memory celltransistors MT2 to MT7. In this case, the situation of FIG. 18 isdifferent from that of FIG. 17 in that most of the thresholds of thenon-selected memory cell transistors MT2 to MT7, which are on thefurther drain side than the memory cell transistor MT1, are greater thanthose in the erase state (according to a write pattern). Therefore, thememory cell transistors MT2 to MT7 are weakly turned on compared to thecase illustrated in FIG. 17. Therefore, the flowing cell current Icell5is smaller than the cell current Icell4 which flows when the programverification is performed.

If so, regardless that the memory cell transistor MT1 passes the programverification, there is a possibility that the memory cell transistor MT1is determined to be an off-cell when data is read. That is, there is apossibility that it is hard to correctly read the data due to thedifference in situations when the program verification is performed andwhen data is read.

Here, a method illustrated in FIG. 19 may be considered. If the methodof FIG. 19 is used, VPVD which is lower than the voltage VREAD isapplied to the word lines WL2 to WL7 which are connected to the memorycell transistors MT2 to MT7 in the erase state when the programverification is performed. If so, the gate potential of the memory celltransistors MT2 to MT7 is lowered compared to the case in FIG. 17, withthe result that the flowing cell current Icell6 is smaller than Icell4,and thus it is possible to set flowing cell current Icell6 toapproximately the same degree as Icell5. That is, if cell current, whichflows when the program verification is performed, and cell current,which flows when data is read, are set to the same degree, it ispossible to correctly read data.

However, when the method is used, it is assumed that data is written inall of the pages (all of the word lines) in the string unit SU. In otherwords, when the program verification is performed, the condition ofvoltage is assuming that data is written in all of the pages. Therefore,if data is not written in all of the pages, it is not possible torealize the same condition when data is read, and thus there is apossibility that erroneous read occurs. In addition, when data iserased, large cell current Icell7 flows through the memory celltransistors MT2 to MT7 which are originally in the erase state asillustrated in FIG. 20, and thus there is a possibility that the memorycell transistors MT2 to MT7 passes the erase verification even when thewritten memory cell transistors MT0 and MT1 are not sufficiently erased.

At this point, in the 3-dimensional stacked NAND flash memory, the wordlines are stacked on the upper side of the semiconductor substrate, andthus it is possible to remarkably improve the degree of integration, ascompared to a planar NAND flash memory in which memory cells are2-dimensionally formed. Instead, the number of pages which are includedin a single string unit SU is significantly large. Therefore, forexample, even when it is sufficient to write data in only a pagecorresponding to the word line WL1, it is necessary to write random datain all of remaining pages. However, it is useless to write the randomdata, and, accordingly, it takes time to write the random data.

Here, according to the embodiment, when data is read, the controller 200provides the information indicative of a word line WL (page), up towhich data is written, to the NAND flash memory 100. Further, the NANDflash memory 100 does not apply an equivalent voltage to all of thenon-selected word lines WL, and applies an appropriate voltage to wordlines WL corresponding to a written area and an unwritten area accordingto the received information. Therefore, it is not necessary to writeuseless data, it is possible to correctly read data, and it is possibleto correctly erase the data. Furthermore, the data write operation canbe shortened due to omitting of writing useless data.

More specifically, when the program verification is performed, VPVDwhich is lower than VREAD is applied to non-selected word lines whichare on the further drain side than the selected word line (refer to FIG.10). Further, when data is read thereafter, VPVD is applied to the wordlines WL corresponding to the unwritten area, and VREAD is applied tothe word line WL corresponding to the written area (refer to FIG. 12).That is, a relatively low voltage VPVD is applied to the gates of thememory cell transistors MT in the erase state which is easily turned onstrongly, and a high voltage VREAD is applied to the gates of the memorycell transistors MT in which data is written and the thresholds thereofmay be raised. Accordingly, even when write is ended in a page in themiddle of the string unit SU, it is possible to set cell current Icell2,which flows when data is read to a value which is equivalent, to thecell current Icell1 which flows when the program verification isperformed. Therefore, it is possible to prevent data from beingerroneously read.

This is the same as when data is erased. For example, as illustrated inFIG. 15, when erase verification is performed, the relationship ofvoltages is set for the word lines WL0 to WL7 in that it is easy to turnon the memory cell transistors MT4 to MT7, which have been already inthe erase state, when data is erased and it is hard to turn on thewritten memory cell transistors MT0 to MT3 which are completely written.Therefore, it is possible to sufficiently reduce the thresholds of thememory cell transistors MT0 to MT3. Otherwise, as illustrated in FIG.16, when data is erased, the relationship of voltages is set for theword lines WL0 to WL7 in that it is relatively hard to reduce thethresholds of the memory cell transistors MT4 to MT7 which have beenalready in the erase state and it is easy to reduce the written memorycell transistors MT0 to MT3 which are completely written. Therefore, itis possible to correctly erase data.

As described above, the semiconductor memory device according to theembodiment includes a plurality of memory cells which are stacked on theupper side of a semiconductor substrate and connected in series, aplurality of word lines which are connected to the gates of theplurality of memory cells, and a row decoder which is connected to theplurality of word lines. When data is read, the row decoder transfers afirst voltage (VPVD in FIG. 12) to non-selected word lines (WL4 to WL7in FIG. 12) that are connected to unprogrammed memory cells, andtransfers a second voltage (VREAD in FIG. 12), which is higher than thefirst voltage, to the non-selected word lines (WL0, WL2, and WL3 in FIG.12) that are connected to the programmed memory cells. Meanwhile, the“unprogrammed memory cells” in the disclosure mean the memory celltransistors that include thresholds at the erase level after data iserased and the programming operation has not been performed yet. Thememory cells in which “0” is written are the “programmed memory cells”.In addition, the memory cell transistors, in which data is written oncebut the data is erased thereafter and the data has not been rewrittenyet, correspond to the “unprogrammed memory cells”.

6. MODIFICATION EXAMPLE

According to the above-described configuration, it is possible toimprove the performance of the semiconductor memory device. However, anembodiment is not limited to the above-described embodiment, and variousmodifications are possible. For example, the write state table 270 isnot limited to information as illustrated in FIG. 5 and may includeinformation indicative of a page up to which data is written, in otherwords, a page which is in the erase state. In addition, the voltagewhich is applied to the word lines WL and which is described withreference to FIGS. 9, 10, 12, and 14 to 16 is an example, and thevoltage is not limited thereto. That is, the voltage is not limited solong as cell current, which flows when program verification isperformed, and the cell current, which flows when the program is read,become the same degree.

In addition, in the embodiment, although the case in which the size ofthe cell current is made an adjustment in both the write operation andthe erase operation is described, a case in which either one of theoperations is made an adjustment may be used.

In addition, in the example of FIG. 4, the case in which the NANDstrings, to which the select gate line SGS is adjacent, are commonlyconnected to each other is described as an example. However, divisionmay be performed on each select gate line SGS such that each select gateline SGS may be independently controlled.

Further, when each of the memory cell transistors MT may hold multi-bitdata (multi-level cell or MLC), the write state table 270 may holdinformation indicative of a bit up to which data is written. Further, avoltage which is applied to non-selected word lines may be determinedaccording to the bit up to which data is written. Such an example willbe described with reference to FIGS. 21 to 24. FIG. 21 is a schematicdiagram illustrating information which is held in the write state table270, and FIGS. 22 to 24 are circuit diagrams illustrating a NAND stringacquired when data is read and illustrating examples in which the memorycell transistors MT may hold two-bit data.

As illustrated in FIG. 21, the write state table 270 holds, for example,information indicative of a word line (page) up to which data is writtenfor each string unit. The example in FIG. 21 illustrates an example inwhich information indicative of whether only a lower bit is written oran upper bit is written for each word line is held. However, it isapparent that the example is not limited to such a table and FIG. 21 isonly a schematic diagram illustrating information which is held in thetable 270. In the example of FIG. 21, the word lines WL0 to WL2 arewritten up to the lower bit and the upper bit, and the word line WL3 iswritten up to only the lower bit.

FIG. 22 is a circuit diagram illustrating a NAND string in which theword line WL2 is selected when data is read, data is written up to theupper bit of the word line WL3, and word lines subsequent to the wordline WL4 are in the erase state. In this case, VREAD or VREADK isapplied to the word line WL3.

FIG. 23 is a circuit diagram illustrating the NAND string in which theword line WL2 is selected when data is read, data is written up to thelower bit of the word line WL3, and the word lines subsequent to theword line WL4 are in the erase state. In this case, VREADL or VREADKL isapplied to the word line WL3. VREADL may have the same value as VREAD ormay have a different value. VREADKL may have the same value as VREADK ormay have a different value.

FIG. 24 is a circuit diagram illustrating the NAND string in which theword line WL2 is selected when data is read, data is written only up tothe word line WL2, and the word lines subsequent to the word line WL3are in the erase state. In this case, VREADE or VREADKE is applied tothe word line WL3. VREADE may have the same value as VREAD and VREADL ormay have a different value. VREADKE may have the same values as VREADKor may have a different value.

As described above, according to the embodiment, it is possible to inputa word line (page), up to which data is written, to the NAND flashmemory from the outside. Therefore, in a case of MLC, it is possible toinput information indicative of the lower/upper page of the word line upto which data is written. Further, the sequencer 116 determines avoltage which is applied to each of the word lines WL based on theinformation. For example, as described above, when a word line WL(n+1)is not written at all, VREADE or VREADKE is applied. When the word lineWL(n+1) is written up to the lower page, VREADL or VREADKL is applied.When the word line WL(n+1) is written up to the upper page, VREAD orVREADK is applied. It is apparent that, this is only an example, anddifferent types of voltage control may be performed.

In addition, the following condition may be assumed. (a) One bit line BLis electrically connected to a plurality of memory strings in one blockBLK. The memory strings includes at least a first memory string and asecond memory string. (b) the write operation is performed for a firstmemory cell transistor MTk in the first memory string at first. Asubsequent write operation is performed for a first memory celltransistor MTk in the second memory string. Next, the write operation isperformed for a second memory cell transistor MT(k+1) in the firstmemory string and for a second memory cell transistor MT(k+1) in thesecond memory string in order. (c) data are written for the memory celltransistors MT0-MT5 in the first memory string. (d) data are written forthe memory cell transistors MT0-MT4 in the second memory string.

In the above condition, we consider a case reading data from the memorycell transistor MT1 in the second memory string. The voltage VDGRV isapplied to the selected word line WL1, the voltage VREADK is applied tounselected word lines WL0 and WL2, the voltage VPVD may be applied tounselected word line WL6 and WL7 only. And the voltage VREAD is appliedto other unselected word lines.

In addition, the memory cell array 111 may be formed on the upper sideof a peripheral circuit such as the row decoder 112 or the senseamplifier 113. That is, the peripheral circuit may be formed on thesemiconductor substrate, the interlayer insulating film may be formed tocover the peripheral circuit, and the well region 20 may be formed onthe interlayer insulating film. Otherwise, the well region 20 may be thesemiconductor substrate. In this case, the row decoder 112 or the senseamplifier 113 is adjacent to the memory cell array 111 and formed on thesemiconductor substrate.

Further, in the embodiment, the case of the 3-dimensional stacked NANDflash memory is described as an example. However, it is possible toapply the embodiment to a planar NAND flash memory. It is apparent thatthere may be a case in which each of the memory cell transistors MTholds data which is equal to or greater than 2 bits. The advantages ofthe embodiment are remarkable when the thresholds of the memory celltransistors MT become high by programming the memory cells.

Meanwhile, in each embodiment,

(1) for example, in a read operation of the memory cell transistorscapable of holding 2-bit data which includes an “E” level, an “A” level,a “B” level, and a “C” level in the ascending order of thresholds, avoltage which is applied to a word line selected in the read operationat the A level is included in a range, for example, between 0 V to0.55V. However, the voltage is not limited thereto and may be includedin any one of ranges between 0.1 V to 0.24 V, 0.21 V to 0.31 V, 0.31 Vto 0.4 V, 0.4 V to 0.5 V, and 0.5 V to 0.55 V.

A voltage, which is applied to the word line selected in the readoperation at the B level, is included in a range, for example, between1.5 V to 2.3 V. However, the voltage is not limited thereto, and thevoltage may be included in any one of ranges, for example, between 1.65V to 1.8 V, 1.8 V to 1.95 V, 1.95 V to 2.1 V, and 2.1 V to 2.3 V.

A voltage, which is applied to the word line selected in the readoperation at the C level, is included in a range, for example, between3.0 V to 4.0 V. The voltage is not limited thereto, and the voltage maybe included in any one of ranges between 3.0 V to 3.2 V, 3.2 V to 3.4 V,3.4 V to 3.5 V, 3.5 V to 3.6 V, and 3.6 V to 4.0 V.

A time (tR) for the read operation may be in ranges, for example,between 25 μs to 38 μs, 38 μs to 70 μs and 70 μs to 80 μs.

(2) A write operation includes a programming operation and averification operation as described above. In the write operation, avoltage, which is initially applied to a word line selected when theprogramming operation is performed, is included in a range, for example,between 13.7 V to 14.3 V. The voltage is not limited thereto, and may beincluded in any one of ranges, for example, between 13.7 V to 14.0 V and14.0 V to 14.6 V.

A voltage, which is initially applied to the selected word line whenwrite is performed on odd-numbered word lines, and the voltage, which isinitially applied to the selected word line when write is performed oneven-numbered word lines, may be changed.

When an Incremental Step Pulse Program (ISPP) method is used for theprogramming operation, for example, approximately 0.5 V may be used asan example of a step-up voltage.

The voltage which is applied to the non-selected word lines may beincluded in a range, for example, between 6.0 V to 7.3 V. The voltage isnot limited thereto and the voltage may be included in a range, forexample, between 7.3 V to 8.4 V or may be equal to or lower than 6.0 V.

A pass voltage to be applied may be changed based on whether thenon-selected word lines are the odd-numbered word lines or theeven-numbered word lines.

A time (tProg) for the write operation may be included in ranges, forexample, between 1,700 μs to 1,800 μs, 1,800 μs to 1,900 μs, and 1,900μs to 2,000 μs.

(3) In the erase operation, the voltage which is initially applied tothe well, which is formed on the upper section of the semiconductorsubstrate and of which the memory cells are arranged on the upper side,is included in a range, for example, between 12 V to 13.6V. The voltageis not limited thereto and may be included in ranges, for example,between 13.6 V to 14.8 V, 14.8 V to 19.0 V, 19.0 to 19.8 V, and 19.8 Vto 21 V.

A time (tErase) for the erase operation may be included in ranges, forexample, between 3,000 μs to 4,000 μs, 4,000 μs to 5,000 μs, and 4,000μs to 9,000 μs.

(4) The memory cells are configured to include a charge storage layerwhich is arranged on a semiconductor substrate (silicon substrate) whileinterposing a tunnel insulating film, which has a film thickness of 4 to10 nm, therebetween. It is possible for the charge storage layer to havea stacked structure of an insulating film, such as SiN or SiON which hasa film thickness of 2 to 3 nm and a ploy-silicon which has a filmthickness of 3 to 8 nm. In addition, metal, such as Ru, may be added topoly-silicon. The insulating film is provided on the charge storagelayer. The insulating film includes, for example, a silicon nitride filmwhich has a film thickness of 4 to 10 nm and which is interposed betweena lower layer High-k film having a film thickness of 3 to 10 nm and anupper layer High-k film having a film thickness of 3 to 10 nm. HfO orthe like may be an example of the High-k film. In addition, it ispossible to cause the film thickness of the silicon nitride film to bethicker than the film thickness of the High-k film. A control electrodewhich has a film thickness of 30 nm to 70 nm is formed on the insulatingfilm while interposing a work function adjusting material, which has afilm thickness of 3 to 10 nm, therebetween. Here, the work functionadjusting material is a metal-oxide film, such as TaO, or a metalnitride film such as TaN. It is possible to use W or the like for thecontrol electrode.

In addition, it is possible to form air gaps between the memory cells.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A semiconductor memory device comprising: aplurality of memory cells that are stacked above a semiconductorsubstrate and are electrically connected in series, the memory cellsincluding first memory cells that are in an erased state and secondmemory cells that are in a programmed state; a plurality of word linesthat are electrically connected to gates of the memory cells; and a rowdecoder that is electrically connected to the word lines, wherein whendata is read from a group of memory cells, the row decoder selects aword line electrically connected to gates of the memory cells in thegroup, transfers a read voltage to the selected word line, transfers afirst voltage to non-selected word lines that are electrically connectedto gates of the first memory cells, and transfers a second voltage,which is different from the first voltage, to non-selected word linesthat are electrically connected to the second memory cells.
 2. Thedevice according to claim 1, wherein the first voltage is at a samevoltage level as a program verification voltage that is applied tomemory cells that are programmed.
 3. The device according to claim 2,wherein the second voltage is higher than the first voltage.
 4. Thedevice according to claim 1, further comprising: a register in whichinformation indicating the word lines connected to the second memorycells is stored.
 5. The device according to claim 4, wherein theregister also stores therein a command and an address at which thecommand is to be executed.
 6. The device according to claim 5, furthercomprising: a control unit configured to control the row decoder totransfer the first or second voltage to the non-selected word linesaccording to the information stored in the register.
 7. The deviceaccording to claim 6, wherein the control unit is a sequencer.
 8. Thedevice according to claim 1, further comprising: first and second selecttransistors electrically connected in series to opposite ends of theplurality of memory cells, such that the memory cells are between thefirst select transistor and the semiconductor substrate and the secondselect transistor is between the memory cells and the semiconductorsubstrate.
 9. The device according to claim 8, further comprising: a bitline, wherein a first end of the first select transistor is electricallyconnected to the bit line and a second end of first select transistor iselectrically connected to the memory cells; and a source line, wherein afirst end of the second select transistor is electrically connected tothe source line and a second end of second select transistor iselectrically connected to the memory cells.
 10. A semiconductor memorydevice comprising: a plurality of memory cells that are stacked above asemiconductor substrate and are electrically connected in series, thememory cells including first memory cells that are in an erased stateand second memory cells that are in a programmed state; a plurality ofword lines that are electrically connected to gates of the memory cells;and a row decoder that applies a voltage to the word lines, wherein whenthe memory cells are erased or erase verification is performed on thememory cells, the row decoder transfers a first voltage to word linesthat are electrically connected to the first memory cells, and transfersa second voltage, which is different from the first voltage, to wordlines which are electrically connected to the second memory cells. 11.The device according to claim 10, wherein the first voltage is higherthan the second voltage.
 12. The device according to claim 10, furthercomprising: a register in which information indicating the word linesconnected to the first memory cells is stored.
 13. The device accordingto claim 12, wherein the register also stores therein a command and anaddress at which the command is to be executed.
 14. The device accordingto claim 13, further comprising: a control unit configured to controlthe row decoder to transfer the first or second voltage to the wordlines according to the information stored in the register.
 15. Thedevice according to claim 14, wherein the control unit is a sequencer.16. The device according to claim 10, further comprising: first andsecond select transistors electrically connected in series to oppositeends of the plurality of memory cells, such that the memory cells arebetween the first select transistor and the semiconductor substrate andthe second select transistor is between the memory cells and thesemiconductor substrate.
 17. The device according to claim 16, furthercomprising: a bit line, wherein a first end of the first selecttransistor is electrically connected to the bit line and a second end offirst select transistor is electrically connected to the memory cells;and a source line, wherein a first end of the second select transistoris electrically connected to the source line and a second end of secondselect transistor is electrically connected to the memory cells.
 18. Amemory controller that controls a semiconductor memory device in whichdata is written in units of a page, comprising: a memory unit thatstores a table that holds information indicating states of pages asbeing programmed or erased; and a control unit configured to issue acommand, wherein the control unit, before issuing the command, transmitsinformation held in the table to the semiconductor memory device. 19.The controller according to claim 18, wherein the command is a readcommand.
 20. The controller according to claim 18, wherein the commandis an erase command.